Page 3 of 22 Transactions on Architecture and Code Optimization

GP-SIMD, a novel hybrid general purpose SIMD architecture, addresses the challenge of data synchronization by in-memory computing, through combining data storage and massive parallel processing. In this paper, we explore a resistive implementation of the GP-SIMD architecture. In resistive GP-SIMD, a novel resistive row and column addressable 4F2 crossbar is utilized, replacing the modified CMOS 190F2 SRAM storage previously proposed for GP-SIMD architecture. The use of the resistive crossbar allows scaling the GP-SIMD from few millions to few hundred millions of processing units on a single silicon die. The performance, power consumption and power efficiency of a resistive GP-SIMD are compared with the CMOS version. We find that PiM architectures and specifically, GP-SIMD, benefit more than other manycore architectures from using resistive memory. A framework for in-place arithmetic operation on a single multi-valued resistive cell is explored, demonstrating a potential to become a building block for next generation PiM architectures.